With many electronic products, security of the data written to and read from memory is important. Examples of such products include portable devices such as cell phones, portable computers, voice recorders, and the like, as well as many larger electronic systems that are utilized in cars, planes, and industrial control systems. To improve security, a processor may be used to encrypt and decrypt data being transferred to and from memory. Typically, a host processor will have access to a memory channel, and the security processor will have access to a separate memory channel. However, for reasons of security, cost, and efficiency, it would be advantageous for the host processor and security processor to have access to the same memory channel.
Normally, where two or more processors share the same memory channel to a memory device, a bus arbiter is required to determine which processor will have access to the memory device at a particular time. However, some processors, such as a processor that eXecutes In Place (XIP), can place significant demands on memory access, as a processor that XIPs can process a significant number of memory reads (e.g., instructions, data), and writes associated with the host processor and must be able to access the memory any time it needs to execute such a memory read or write, or else it will crash. When a processor that XIPs is utilized in a multi-processor system where the processors all share a single channel to access a memory device, bus arbitration can become complicated, if not unworkable. Thus, where a host processor that XIPs and security processor share a single channel (bus) to access a memory device, it would be advantageous for the host processor to have access to the memory device any and every time it needs to execute a memory read or write associated with the host processor, while also allowing the security processor to access the memory device to read or write data from the memory device and perform its co-processing functions.